1. Field of the Invention
The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a package assembly that includes a system on a chip (SoC) and memory die coupled to a BGA (ball grid array) substrate.
2. Description of Related Art
Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages to be coupled to printed circuit boards (PCBs). PoP packages, however, are still limited in the minimum thicknesses (z-heights) that may be achieved (e.g., current techniques may only achieve z-heights of about 1.2 to about 1.3 mm above the PCB).
In addition, PoP packages provide little to no thermal separation between the SoC and its associated memory die (e.g., DRAM die) because the memory die are stacked near the SoC. Because the SoC and its associated memory die are thermally coupled, heat generated from the SoC may heat the memory die and the memory die is slowed down (throttled) to inhibit overheating of the memory die. Additionally, heat generated from the memory die may heat the SoC because the SoC and its associated memory die are thermally coupled, thus slowing down the SoC. The issues with thermal coupling and thermal density between the SoC and the memory die may be further increased as z-height in PoP packages (or similarly stacked package topologies) is reduced. Because of these issues with PoP packages, potential advancements and/or design modifications are being developed to provide semiconductor package assemblies using SoCs that can reduce z-height (thickness) as well as provide improved thermal properties for the SoC and/or the memory die. Additional advancements are also being developed to integrate power delivery systems into the package assembly and improve signal integrity to memory die at higher speeds.